1. Field of the Invention
The present invention relates generally to the field of computer memory, and, more particularly, to an apparatus and method for integrated functional built-in self test for an ASIC.
2. Description of the Related Art
Integrated circuit operational speeds (i.e., signal frequencies) often outpace even the most advanced test equipment. Moreover, these chips often have complex internal state structures with significant embedded memory arrays.
An embedded dynamic random access memory (“EDRAM”) data cache chip typically contains the following: an on-chip EDRAM section, which comprises one or more EDRAM macro units; a command logic section to interpret the cache chip data access commands; a write logic section to buffer and write the incoming data into the EDRAM; and a read logic section to read out the data from the EDRAM. Each logic section typically includes a corresponding off-chip interface unit. The off-chip interface section typically includes the following: receivers unit for the command bus; receivers unit for the write data bus; and drivers unit for the read data bus. One or more sets of these off-chip interface units may be on a chip to provide for additional data bandwidth, data throughput, or to provide for concurrent data sharing among more than one processor chip. Solely for the sake of simplicity, a single off-chip interface unit is assumed.
An exemplary existing implementation for an EDRAM chip includes a pseudorandom memory address and data test. The logic of the EDRAM chip may also include the following: traditional deterministic dynamic random access memory (“DRAM”) tests (e.g., marching 0's, 1's, stripes, gallops, etc.); a single bit error injected in the command bus and write data bus; a check for corrected data after error injection; memory scrub and fill; and a power saving standby mode memory refresh control.
The prior art of chip or system testing can be characterized as performing one of the following types of tests: a scan test, a pseudo random logic test (described in U.S. Pat. No. 5,369,648 to Nelson, entitled “Built-in Self-Test Circuit”), or random access memory (“RAM”) array test (described in U.S. Pat. No. 5,617,531 to Crouch, entitled “Data Processor Having a Built-In Internal Self Test Controller for Testing a Plurality of Memories Internal to the Data Processor”). These techniques are undesirable because they do not test the chip in the way it is used in the system (e.g., at design target speed with many simultaneously switching signals, at system power and thermal conditions, etc.). Further, a number of the existing test methods rely upon very expensive external chip or system testers.